The present invention relates to delay-locked loop (DLL) circuits. More particularly, this invention relates to DLL circuits for use in, for example, programmable logic devices (PLDs) or semiconductor memory devices for providing adjustable phase shift control of a DLL clock signal using a processed control signal.
In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. It is known to incorporate one or more DLL circuits into PLDs to achieve a certain phase shift between clock and data signals as required by many different applications (e.g., for several memory interface standards). Alternatively, DLL circuitry may be incorporated directly into semiconductor memory devices or other types of circuitry. For example, a DLL circuit may be used to provide a data input/output timing signal, or data strobe signal (DQS), that is phase shifted with respect to an external, or reference clock signal. In turn, this phase shifted DQS may be used for clocking data into and out of a memory device during respective write and read cycles.
A conventional DLL circuit that provides a phase shifted DLL control signal based on a reference clock signal may include a pair of variable delay circuits (e.g., a main variable delay circuit and a second, smaller variable delay circuit), a phase detector and an up down counter that provides the main and smaller variable delay circuits with a main control signal. The phase detector compares the reference clock signal with a delayed version of the reference clock signal, or internal clock signal, that is produced by the main variable delay circuit. Based on this comparison, the phase detector either increments or decrements the up down counter. In response, the main control signal produced by the up down counter is adjusted to either increase or decrease the delay setting of the main variable delay circuit. This process repeats, with the internal clock signal coming closer in phase to the reference clock signal following each adjustment to the delay setting of the main variable delay circuit.
Once the DLL circuit is locked (i.e., the internal clock signal and the reference clock signal are in phase), the main control signal is set such that the delay by the main variable delay circuit is equal to one complete clock cycle of the reference clock signal. At this time, the main control signal is also used to control the delay setting of the smaller variable delay circuit, which provides a certain phase shift to a DQS. Depending on the relative sizes of the main and smaller variable delay circuits (e.g., the number of delay stages in the smaller variable delay circuit compared to the number of delay stages in the main variable delay circuit), a particular phase shifted DQS is generated.
With conventional DLL circuits such as described above, the phase shift for DQS when the DLL circuit is locked is not adjustable once the size relationship between the main and smaller variable delay circuits is set. For example, if the frequencies of the reference clock signal and the DLL clock signal are substantially identical, and the smaller variable delay circuit is one-fourth the size of the main variable delay circuit, then the DLL clock signal will be shifted by one-fourth of a complete clock cycle (i.e., 90°) when the DLL circuit is locked. Many applications, however, require the phase shift of a DLL clock signal (e.g., a DQS) to be adjustable even after the size relationship between the main and smaller variable delay circuits is set.
Therefore, DLL circuitry is needed that is capable of providing a DQS or other type of DLL clock signal with adjustable phase shift even after the size relationship between the main and smaller variable delay circuits has been set.